1. The Field of the Invention
The present invention relates to fabrication of semiconductor structures. More particularly, the present invention relates to formation of semiconductor structures by ion implantation techniques. In particular, the inventive method disclosed herein is applied to formation of a complementary metal oxide semiconductor structure that includes formation of ion-implant enhanced isolation trenches for electrical isolation of active areas. The invention is applicable to formation of semiconductor structures that require two dopants that are different or opposite in conductivity enhancement of semiconductor silicon.
2. The Relevant Technology
In the microelectronics industry, a substrate refers to one or more semiconductor layers or structures which includes active or operable portions of semiconductor devices. In the context of this document, the term xe2x80x9csemiconductive substratexe2x80x9d is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term substrate refers to any supporting structure including but not limited to the semiconductive substrates described above.
In the microelectronics industry, the process of miniaturization entails shrinking the size of individual semiconductor devices and crowding more semiconductor devices into a given unit area than has been previously achieved. With miniaturization, problems of device crowding arise. For example, problems of proper isolation between components arise. When miniaturization demands the shrinking of individual devices, isolation structures must also be reduced in size.
To form an isolation trench, a photoresist material is applied to a semiconductive material into which the isolation trench is to be formed, preferably by etching the semiconductive material. A beam of light, such as ultraviolet (UV) light, transfers a pattern through an imaging lens from a photolithographic template to the photoresist material. The pattern of the photolithographic template includes opaque and transparent regions with selected shapes that match corresponding openings and intact portions intended to be formed in the photoresist material. The photolithographic template is conventionally designed by computer-assisted drafting and is of a much larger size than the semiconductor structure on which the photoresist material is located. Light is directed through the photolithographic template and is focused on the photoresist coating in a manner that reduces the pattern of the photolithographic template to the size of the photolithographic coating and that develops the portions of the photoresist coating that are unmasked and are intended to remain. The undeveloped portions are thereafter easily removed. Other photolithographic techniques for formation of semiconductor structures are also possible. After the removal of the undeveloped portions of the photoresist material, the isolation trench is etched into the semiconductive material.
Isolation trenches and active areas are often doped, either to enhance conductivity around an isolation area, to increase the breakdown voltage (BV) of an active area diode which is adjacent to a field isolation trench, and/or to achieve a higher threshold voltage (VT) of a parasitic field transistor.
For the fabrication of a complimentary metal oxide semiconductor (CMOS) device, ion implantation is used to form a preferred BV of an active area diode and a preferred VT a parasitic field transistor. The BV and VT are achieved by patterning a first mask on an N-well side of the CMOS device being fabricated. Next, dopant ions are implanted into the P-well portion of the device. Following dopant ion implantation of the P-well, the mask must be removed and the CMOS device must be patterned with a second mask on the P-well side of the CMOS device being fabricated. After patterning of the second mask, the N-well is implanted with dopant ions. This first and second mask technique is required to prevent the wrong type of dopant in each of the N-well and P-well of the CMOS device being fabricated.
The first and second mask process involves several steps which increase the possibility for fabrication errors entering into the process flow that will lower overall production yield. For example, where an isolation trench was formed by an anisotropic etch, a portion of the first mask is polymerized to begin to line the recess formed by the anisotropic etch. In such a case, stripping of the first photoresist may require a stronger stripping solution than would otherwise be needed. During photoresist polymerization, the polymerized photoresist may combine with other exposed portions of the semiconductor structure, such as contaminants, and thereby form a polymer composite film within the recess being formed. Such a polymer composite film resists stripping with conventional stripping solutions. A more effective stripping solution, however, that removes a polymer composite film will likely also cause undesirable topographies of the semiconductor structure that may compromise the integrity thereof.
What is needed is a method of ion implantation in a CMOS semiconductor structure being fabricated that achieves complimentary ion implantation with minimized masking steps in order to improve overall production yield. What is also needed is a method of CMOS fabrication that reduces destructive doping in N-well and P-well portions of a CMOS structure being fabricated while minimizing the number of masking steps.
The present invention relates to doping of a semiconductor structure using a minimal number of masks. By way of illustration, the present invention relates to the formation of trench isolation structures that isolate active areas, and relates to preferred doping in the fabrication of a CMOS device with use of a minimal number of masks. Other uses for the inventive method may include CMOS formation with field oxide regions used to separate active areas. The inventive method can be used in the fabrication or CMOS device including such structures as dynamic random-access memory (DRAM) structures, word line-activated transistors, and bipolar transistors.
In the inventive method, an isolation trench is formed in each of a P-well and an N-well, where the P-well and the N-well are situated in a semiconductor material. Each isolation trench extends below a top surface of the semiconductor material upon which is situated a pad oxide, a nitride layer, and a photoresist layer having a pattern therein through which an etchant anisotropically etched the semiconductor material so as to form the isolation trenches in each of the P-well and the N-well.
A first doping scheme is a doping of the semiconductor material with a P-type dopant, such as boron. The P-well and the N-well are both doped by ion implantation with the P-type dopant, which may include multiple doping steps. In the first doping scheme, the ions are implanted through the pad oxide, the nitride layer, and the photoresist layer into the semiconductor material. Ions that are implanted into the isolation trenches in each of the P-well and the N-well will implant deeper into the semiconductor material than ions that are implanted through the pad oxide, the nitride layer, and a photoresist layer.
The first doping scheme will preferably be two ion implantations that produce a first and a second P-type dopant concentration profile. The second P-type dopant concentration profile dopes active areas in each of the P-well and the N-well. Also, the second P-type dopant concentration profile has a beginning and ending that is deeper within the semiconductor material at comparable portions of the semiconductor material than that of the first P-type dopant concentration profile. As such, the first and second P-type dopant concentration profiles appears at differing levels at comparable portions of the semiconductor material due to the lesser energy of the first ion implantation compared to that of the second ion implantation. As such, the relative energy levels dictate the ability of the second ion implantation and the disability of the first ion implantation to penetrate through the pad oxide, the nitride layer, and the photoresist layer into the semiconductor material. The order of the first and second ion implantations can be reversed.
Following the second ion implantation, a thermal process is carried out to migrate implanted dopants into the semiconductor material, the effect of which is to flatten the first and second P-type dopant concentration profiles. A thermal oxide layer is grown in the isolation trenches of the P-well and N-well during the thermal process, and each isolation trench is filled with a dielectric material. A planarizing step then reduces the height of the structure. Next, the photoresist layer and the nitride layer are removed, leaving the dielectric material extending from each isolation trench above the pad oxide layer.
A second mask is formed over the P-well, leaving exposed the N-well of the CMOS device being fabricated. The second mask has a thickness that is selected to substantially resist ion penetration therethrough into the P-well. Next, a second doping scheme is carried out as a doping of the N-well with an N-type dopant, such as phosphorous. The second doping scheme dopes active areas adjacent to trenches in the N-well. A multiple number or ion implantations of variable energy are carried out in the doping of the N-well. As the N-well was doped with P-type dopants in the first doping scheme, the second doping scheme is sufficient to overcome the P-type dopant effect with N-type dopants. The first and second doping schemes will preferably assist in electrical isolation of active areas in each of the P-well and N-well so as to reduce leakage currents.
Energy of the implantations of the first and second doping schemes can be controlled to achieve a preferred voltage threshold (VT) for a parasitic field transistor through selected dopant concentration profiles. For example, selected energies of the ion implantations can be designed to achieve a preferred trench wall and trench well implant concentration profiles, as well as a preferred deep junction implant concentration profile. Following preferred implantations, the second mask is removed as is the pad oxide layer, and a gate oxide layer in place thereof. A process flow is then conducted so that the desired CMOS structure is completed.
These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.